Welcome to Ch BP Govt. Engineering College, Jaffarpur

SOFTWARE ENGINEERING LAB

 

COURSES OFFERED

ETEC-351 Digital Circuit & System-II
ETIT-360   Digital Communication –II
ETIT-358  Data Warehousing & Data Mining Lab
ETIT-455 Advanced Computer Network

 

             

EQUIPMENTS AVAILABLE

Sl.No.

Name of Equipment

Quantity/Number

1.

Computer (Wipro, HP)

30

2.

Dot Matrix Printer

01

3.

MultiMedia Projector

01

4.

Hp Scanjet 2480 Scanner

01

5.

Software:

OrCad

01

6. ADVANCED COMPUTING NETWORK LAB
1.

BenchMark Security Kit

NETSYS Router  and FireWall

LAN Trainer Kit

01
2.
05
3.
05

EXPERIMENTS

ETEC-351                   :           Digital Circuit & System-II

DATAFLOW MODELING

  1. Implement And & Or Gate In Vhdl Using Dataflow Modeling.
  2. Implement Xor Gate Vhdl Using Dataflow Modeling.
  3. Implement Xnor Gate Vhdl Using Dataflow Modeling.
  4. Implement Half Adder In Vhdl Using Dataflow Modeling.
  5. Implement Full Adder In Vhdl Using Dataflow Modeling.
  6. Implement Full Subtractor In Vhdl Using Dataflow Modeling.
  7. Implement Half Subtractor In Vhdl Using Dataflow Modeling.
  8. Implement 4:2 Encoder In In Vhdl Using Dataflow Modeling.
  9. Implement 2:4 Decoder  In Vhdl Using Dataflow Modeling.
  10. Implement Multiplexer In Vhdl Using Dataflow Modeling.
  11. Implement Demultiplexer In Vhdl Using Dataflow Modeling.
  12. Implement Sr Ff In Vhdl Using Dataflow Modeling.
  13. Implement Jk Ff In Vhdl Using Dataflow Modeling.
  14. Implement D  Ff In Vhdl Using Dataflow Modeling.
  15. Implement T Ff In Vhdl Using Dataflow Modeling.
  16. Implement  D Ff In Vhdl Using Dataflow Modeling.
  17. Implemnt 3-Bit Shift Register  In Vhdl Using Dataflow Modeling.

Structural  Modeling

  1. Implement And & Or Gate In Vhdl Using Dataflow Modeling.
  2. Implement Xor Gate Vhdl Using Dataflow Modeling.
  3. Implement Xnor Gate Vhdl Using Dataflow Modeling.
  4. Implement Half Adder In Vhdl Using Dataflow Modeling.
  5. Implement Full Adder In Vhdl Using Dataflow Modeling.
  6. Implement Full Subtractor In Vhdl Using Dataflow Modeling.
  7. Implement Half Subtractor In Vhdl Using Dataflow Modeling.
  8. Implement 4:2 Encoder In In Vhdl Using Dataflow Modeling.
  9. Implement 2:4 Decoder  In Vhdl Using Dataflow Modeling.
  10. Implement Multiplexer In Vhdl Using Dataflow Modeling.
  11. Implement Demultiplexer In Vhdl Using Dataflow Modeling.
  12. Implement Sr Ff In Vhdl Using Dataflow Modeling.
  13. Implement Jk Ff In Vhdl Using Dataflow Modeling.
  14. Implement D  Ff In Vhdl Using Dataflow Modeling.
  15. Implement T Ff In Vhdl Using Dataflow Modeling.
  16. Implement  D Ff In Vhdl Using Dataflow Modeling.
  17. Implemnt 3-Bit Shift Register  In Vhdl Using Dataflow Modeling.

Behavioral Modeling

  1. Implement And & Or Gate In Vhdl Using Dataflow Modeling.
  2. Implement Xor Gate Vhdl Using Dataflow Modeling.
  3. Implement Xnor Gate Vhdl Using Dataflow Modeling.
  4. Implement Half Adder In Vhdl Using Dataflow Modeling.
  5. Implement Full Adder In Vhdl Using Dataflow Modeling.
  6. Implement Full Subtractor In Vhdl Using Dataflow Modeling.
  7. Implement Half Subtractor In Vhdl Using Dataflow Modeling.
  8. Implement 4:2 Encoder In In Vhdl Using Dataflow Modeling.
  9. Implement 2:4 Decoder  In Vhdl Using Dataflow Modeling.
  10. Implement Multiplexer In Vhdl Using Dataflow Modeling.
  11. Implement Demultiplexer In Vhdl Using Dataflow Modeling.
  12. Implement Sr Ff In Vhdl Using Dataflow Modeling.
  13. Implement Jk Ff In Vhdl Using Dataflow Modeling.
  14. Implement D  Ff In Vhdl Using Dataflow Modeling.
  15. Implement T Ff In Vhdl Using Dataflow Modeling.
  16. Implement  D Ff In Vhdl Using Dataflow Modeling.
  17. Implemnt 3-Bit Shift Register  In Vhdl Using Dataflow Modeling.
  18. Implement Bcd To Gray Code Converter.
  19. Design A Binary Multiplier
  20. Design An Alu For Performing Add,Sub, Multiplication And Division
  21. Design An Even Bit Parity Checker With State Diagram And Transition Tables.

 

ETIT-360                    :           Digital Communication –II

  1. Write A C Program To Calculate Source Entropy And Information Rate.
  2. Write A C Program To Perform Shanon-Fano Coding An D Calculate Efficiency.
  3. Convolution Codes.
  4. Write A C Program To:-
  5. Obtain The Generator Matrix(A)
  6. List All The Code Vectors Of A Given Matrix Whose Parity Check Matrix Is Given
  7. The Generate Matrix For A(6,3) Block Code Is Given Below. Obtain All The Code Of Words Of This Code.
  8. The Generate Polynomial Of(7,4) Cyclic Code Is G(P)=P^3+P+1. Obtain All The Code Vectors For The Code In Non- Systematic Form.

 

ETIT-358        :           Data Warehousing and Data Mining Lab

  1. Study of weka tool:-

--introduction to weka.
--launching of weka
--the weka explorer
--classification
2.          Examples:-
                              --for weather forecasting
                              --to generate database
                              -- creating confusion matrix
                              --creating decision tree  
3.          For prescription of optical lenses
                              -- to generate database
                              -- creating confusion matrix
                              --creating decision tree

 

 

 
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